MCM62Y308 Datasheet, PDF (1/16 Pages) Motorola, Inc – Synchronous Line Buffer:8K x 8 Bit Fast Static Dual Ported Memory

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SEMICONDUCTOR TECHNICAL DATA
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Advance Information
MCM62Y308
Synchronous Line Buffer:
8K x 8 Bit Fast Static Dual
Ported Memory
With IEEE Standard 1149.1 Test Access Port
and Boundary–Scan (JTAG)
32
1
J PACKAGE
300 MIL SOJ
CASE 857–02
The MCM62Y308 is a synchronous, dual ported memory organized as 8,192
words of 8 bits each, fabricated using Motorola’s double–metal, double–poly,
0.65 µm CMOS process. It is intended for high speed video or other applications
which process data on a line–by–line basis. Through the use of a single clock and
port control inputs, separate read and write data ports provide simultaneous ac-
cess to a common memory array. Simultaneous read/write access to the same
address location is also allowed, with old data being read followed by a write of
the new data. This allows multiple devices to be cascaded with the output of one
directly driving the input of another. In this configuration the data stream can be
tapped at strategic interconnect points to perform various digital filtering functions.
Since there are no external address inputs, separate internal read and write
address counters are provided as a means of indexing the memory array. These
counters are preloaded and then selectively incremented or decremented by
asserting read enable (RE) and write enable (WE) inputs, allowing cycle to cycle
control. The address counters can be reloaded back to their initial values through the
use of the read reload (RR) and write reload (WR) control inputs. These inputs
initiate the transfer of address reload register values into the address counters which
index the memory array. When an address counter reaches 0000 it will roll over on
the next count. On the down count the roll over condition will cause the roll–over flag
(WRF or RRF) to assert high. On the up count these flags must be treated as don’t
cares. The roll–over flag outputs are cleared when their associated roll–over reset
pin is asserted low. The TDI input is used to write the reload registers using special
test access port instructions.
The read and write address counters are 16 bits long, and only 13 of the 16 bits
are required to index the 8K deep memory array. The remaining three bits are
used for depth expansion. These three bits are compared to the lower three bits
in the control register, and as long as they are equal that port (i.e., read or write)
will remain active. If the bits do not compare, the port will become inactive (i.e.,
for read outputs, high–z; for write inputs, disabled) however, the counter will
continue to count on the rising edge of K as long as the port enable signal (RE or
WE) is asserted. The TDI input is used to write the control register using special
test access port instructions.
The output enable Input can be programmed to be either synchronous or
asynchronous through the control register.
The MCM62Y308 is available in a 32 pin SOJ package.
• 8K x 8 Fast Access Static Memory Array
• Single 5 V Power Supply — MCM62Y308–17: ± 5%
• Synchronous, Simultaneous Read/Write Memory Access
• 50 MHz Maximum Clock Cycle Time, < 15 ns Read Access
• Single Clock Operation
• Separate Read/Write Address Counters with Reload Control
• Separate Up/Down Counter Control for Both Read and Write
• Separate Roll–Over Flag Outputs for Read and Write
• Programmable Output Enable Control (Synchronous or Asynchronous)
• Cascadable I/O Interface
• IEEE Standard 1149.1 Test Port (JTAG)
• Expand ID Register for Depth Expansion
• High Board Density SOJ Package
PIN ASSIGNMENT
WRR 1
D7 2
D6 3
D5 4
D4 5
D3 6
D2 7
D1 8
D0 9
VDD 10
K 11
WE 12
WR ₁₃
TDI 14
TCK 15
RRR 16
32 WRF
31 Q7
30 Q6
29 Q5
28 Q4
27 Q3
26 Q2
25 Q1
24 Q0
23 VSS
22 G
21 RE
20 RR
19 TDO
18 TMS
17 RRF
PIN NAMES
K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
WE . . . . . . . . . . . . . . . . . . Write Enable Input
WR . . . . . . . . . . Write Address Reload Input
RE . . . . . . . . . . . . . . . . . .Read Enable Input
RR . . . . . . . . . Read Address Reload Input
RRF . . . . . . . . Read Roll–Over Flag Output
WRF . . . . . . . Write Roll–Over Flag Output
RRR . . . . . . . . Read Roll–Over Reset Input
WRR . . . . . . . Write Roll–Over Reset Input
G . . . . . . . . . . . . . . . . . Output Enable Input
D0 – D7 . . . . . . . . . . . . . . . . . . . . Data Inputs
Q0 – Q7 . . . . . . . . . . . . . . . . . . Data Outputs
TCK . . . . . . . . . . . . . . . . . . . Test Clock Input
TMS . . . . . . . . . . . . . . . . . . Test Mode Select
TDI . . . . . . . . . . . . . . . . . . . . Test Data Input
TDO . . . . . . . . . . . . . . . . . . Test Data Output
VDD . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
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MCM62Y308
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