MCM6265C Datasheet, PDF (1/8 Pages) Motorola, Inc – 8K x 9 Bit Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8K x 9 Bit Fast Static RAM
The MCM6265C is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual–in–line and plastic small–outline J–leaded packages.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• Fast Access Times: 12, 15, 20, 25, and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
• Low Power Operation: 110 – 150 mA Maximum AC
• Fully TTL Compatible — Three State Output
A2
A3
A4
A5
A7
A9
A10
A11
DQ0
DQ8
BLOCK DIAGRAM
ROW
DECODER
VCC
VSS
MEMORY MATRIX
256 ROWS x 32
x 9 COLUMNS
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
A0 A1 A6 A8 A12
E1
E2
W
G
Order this document
by MCM6265C/D
MCM6265C
P PACKAGE
300 MIL PLASTIC
CASE 710B–01
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
A8 1
A7 2
A6 3
A5 4
A4 5
A3 6
A2 7
A1 8
A0 9
DQ0 10
DQ1 11
DQ2 12
DQ3 ₁₃
VSS 14
28 VCC
27 W
26 E2
25 A9
24 A10
23 A11
22 G
21 A12
20 E1
19 DQ8
18 DQ7
17 DQ6
16 ^DQ5
15 DQ4
PIN NAMES
A0 – A12 . . . . . . . . . . . . . Address Input
DQ0 – DQ8 . . . Data Input/Data Output
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2 . . . . . . . . . . . . . . . . . Chip Enable
VCC . . . . . . . . . . . Power Supply (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 2
5/95
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MCM6265C
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