MCM6249 Datasheet, PDF (1/7 Pages) Motorola, Inc – 1M x4 Bit Static Random Access Memory

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM6249/D
1M x 4 Bit Static Random
Access Memory
The MCM6249 is a 4,194,304 bit static random access memory organized as
1,048,576 words of 4 bits, fabricated using high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6249 is equipped with chip enable (E) and output enable (G) pins,
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high impedance.
The MCM6249 is available in a 400 mil, 32–lead surface–mount SOJ package.
• Single 5 V ± 10% Power Supply
• Fast Access Time: 20/25/35 ns
• Equal Address and Chip Enable Access Time
• All Inputs and Outputs are TTL Compatible
• Three–State Outputs
• Power Operation: 190/175/160 mA Maximum, Active AC
BLOCK DIAGRAM
A13
A12
A11
A10
A9
A8
ROW
DECODER
MEMORY MATRIX
1024 ROWS x
4096 COLUMNS
A7
A6
A5
A4
DQ0
COLUMN I/O
INPUT
COLUMN DECODER
DATA
CONTROL
DQ3
A18 A17 A16 A15 A14 A19 A3 A2 A1 A0
DQ0
E
W
DQ3
G
MCM6249
WJ PACKAGE
400 MIL SOJ
CASE 857A–02
PIN ASSIGNMENT
A7 ₁
A8 2
A9 ₃
A17 ₄
A6 ₅
E₆
DQ0 7
VCC 8
VSS 9
DQ1 ₁₀
W ₁₁
A13 12
A18 13
A10 14
A11 ¹⁵
A12 16
32 ^A1
31 ^A0
30 ^A5
29 ^A4
28 ^A19
27 ^G
26 ^DQ3
25 ^VSS
24 ^VCC
23 ^DQ2
22 ^A2
21 ^A16
20 ^A15
19 ^A14
18 ^A3
17 NC
PIN NAMES
A0 – A19 . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ0 – DQ3 . . . . . . . . Data Input/Output
NC . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 4
5/95
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MCM6249
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