MCM6227B Datasheet, PDF (1/8 Pages) Motorola, Inc – 1M x 1 Bit Static Random Access Memory

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1M x 1 Bit Static Random
Access Memory
The MCM6227B is a 1,048,576 bit static random–access memory organized
as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability.
The MCM6227B is each equipped with a chip enable (E) pin. This feature pro-
vides reduced system power requirements without degrading access time per-
formance.
The MCM6227B is available in 300 mil and 400 mil, 28–lead surface–mount
SOJ packages.
• Single 5 V ± 10% Power Supply
• Fast Access Times: 15/17/20/25/35 ns
• Equal Address and Chip Enable Access Times
• Input and Output are TTL Compatible
• Three–State Output
• Low Power Operation: 115/110/105/100/95 mA Maximum, Active AC
BLOCK DIAGRAM
A
A
A
A
A
ROW
DECODER
A
A
A
A
MEMORY MATRIX
512 ROWS x
2048 x 1 COLUMNS
D
INPUT
DATA
COLUMN I/O
Q
CONTROL
COLUMN DECODER
E
A A A A A A A A AA A
W
Order this document
by MCM6227B/D
MCM6227B
J PACKAGE
300 MIL SOJ
CASE 810B–03
WJ PACKAGE
400 MIL SOJ
CASE 810–03
PIN ASSIGNMENT
A1
A2
A3
A4
A5
A6
NC 7
A8
A9
A 10
A 11
Q 12
W 13
VSS ₁₄
28 ^VCC
27 ^A
26 A
25 A
24 A
23 A
22 A
21 NC*
20 ^A
19 A
18 A
17 A
16 D
15 E
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
D . . . . . . . . . . . . . . . . . . . . . . . . Data Input
Q . . . . . . . . . . . . . . . . . . . . . Data Output
NC . . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
*If not used for no connect, then do not ex-
ceed voltages of – 0.5 to VCC + 0.5 V.
This pin is used for manufacturing diag-
nostics.
REV 3
10/31/96
M^© O^MoT^toO^roR^la,O^InL^c.A¹⁹F⁹⁴AST SRAM
MCM6227B
1