MCM6227A Datasheet, PDF (1/8 Pages) Motorola, Inc – 1M x 1 Bit Static Random Access Memory

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1M x 1 Bit Static Random
Access Memory
The MCM6227A is a 1,048,576 bit static random–access memory organized
as 1,048,576 words of 1 bit, fabricated using high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes while CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6227A is equipped with a chip enable (E) pin. In less than a cycle time
after E goes high, the part enters a low–power standby mode, remaining in that
state until E goes low again.
The MCM6227A is available in 400 mil, 28–lead surface–mount SOJ pack-
ages.
• Single 5 V ± 10% Power Supply
• Fast Access Times: 20, 25, 35, and 45 ns
• Equal Address and Chip Enable Access Times
• Input and Output are TTL Compatible
• Three–State Output
• Low Power Operation: 160/140/130/120 mA Maximum, Active AC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D
E
W
BLOCK DIAGRAM
VCC
VSS
ROW
DECODER
MEMORY MATRIX
1024 ROWS x
1024 COLUMNS
INPUT
COLUMN I/O
Q
DATA
CONTROL
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Order this document
by MCM6227A/D
MCM6227A
WJ PACKAGE
400 MIL SOJ
CASE 810–03
PIN ASSIGNMENT
A0 1
A1 2
A2 3
A3 ₄
A4 5
A5 6
NC 7
A6 8
A7 9
A8 10
A9 11
Q 12
W 13
VSS ₁₄
28 ^VCC
27 ^A19
26 A18
25 A17
24 A16
23 A15
22 A14
21 NC
20 ^A13
19 A12
18 A11
17 A10
16 D
15 E
PIN NAMES
A0 – A19 . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
D . . . . . . . . . . . . . . . . . . . . . . . . Data Input
Q . . . . . . . . . . . . . . . . . . . . . Data Output
NC . . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 4
5/95
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MCM6227A
1