MCM6226BB Datasheet, PDF (1/8 Pages) Motorola, Inc – 128K x 8 Bit Static Random Access Memory

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
128K x 8 Bit Static Random
Access Memory
The MCM6226BB is a 1,048,576 bit static random access memory organized
as 131,072 words of 8 bits. Static design eliminates the need for external clocks
or timing strobes while CMOS circuitry reduces power consumption and provides
for greater reliability.
The MCM6226BB is equipped with both chip enable (E1 and E2) and output
enable (G) pins, allowing for greater system flexibility and eliminating bus conten-
tion problems.
The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mount
SOJ packages.
• Single 5 V ± 10% Power Supply
• Fast Access Times: 15/17/20/25/35 ns
• Equal Address and Chip Enable Access Times
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC
BLOCK DIAGRAM
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
512 ROWS x
2048 COLUMNS
A
A
A
A
DQ
INPUT
COLUMN I/O
DATA
DQ
CONTROL
COLUMN DECODER
E1
E2
A A A AA AA A
W
G
Order this document
by MCM6226BB/D
MCM6226BB
XJ PACKAGE
400 MIL SOJ
CASE 857A–02
EJ PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
NC 1
A2
A3
A4
A5
A6
A7
A8
A9
A 10
A 11
A 12
DQ 13
DQ 14
DQ 15
VSS ₁₆
32 ^VCC
31 ^A
30 E2
29 ^W
28 ^A
27 ^A
26 ^A
25 A
24 ^G
23 A
22 E1
21 DQ
20 DQ
19 DQ
18 DQ
17 ^DQ
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2 . . . . . . . . . . . . . . . . Chip Enables
DQ . . . . . . . . . . . . . Data Inputs/Outputs
NC . . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 2
10/31/96
M^© O^MoT^toO^roR^la,O^InL^c.A¹⁹F⁹⁶AST SRAM
MCM6226BB
1