MCM62110 Datasheet, PDF (1/12 Pages) Motorola, Inc – 32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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by MCM62110/D
32K x 9 Bit Synchronous Dual I/O
or Separate I/O Fast Static RAM
with Parity Checker
MCM62110
The MCM62110 is a 294,912 bit synchronous static random access memory
organized as 32,768 words of 9 bits, fabricated using Motorola’s high–perfor-
mance silicon–gate CMOS technology. The device integrates a 32K x 9 SRAM
core with advanced peripheral circuitry consisting of address registers, two sets
of input data registers, two sets of output latches, active high and active low chip
enables, and a parity checker. The RAM checks odd parity during RAM read
cycles. The data parity error (DPE) output is an open drain type output which indi-
cates the result of this check. This device has increased output drive capability
supported by multiple power pins. In addition, the output levels can be either 3.3 V
or 5 V TTL compatible by choice of the appropriate output bus power supply.
The device has both asynchronous and synchronous inputs. Asynchronous
inputs include the processor output enable (POE), system output enable (SOE), and
the clock (K).
The address (A0 – A14) and chip enable (E1 and E2) inputs are synchronous
and are registered on the falling edge of K. Write enable (W), processor input
enable (PIE) and system input enable (SIE) are registered on the rising edge
of K. Writes to the RAM are self–timed.
All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP
have input data registers triggered by the rising edge of the clock. These pins also
have three–state output latches which are transparent during the high level of the
clock and latched during the low level of the clock.
This device has a special feature which allows data to be passed through the
RAM between the system and processor ports in either direction. This streaming
is accomplished by latching in data from one port and asynchronously output
enabling the other port. It is also possible to write to the RAM while streaming.
Additional power supply pins have been utilized for maximum performance. The
output buffer power (VCCQ) and ground pins (VSSQ) are electrically isolated from
VSS and VCC, and supply power and ground only to the output buffers. This allows
connecting the output buffers to 3.3 V instead of 5.0 V if desired. If 3.3 V output levels
are chosen, the output buffer impedance in the ‘‘high’’ state is approximately equal
to the impedance in the ‘‘low’’ state thereby allowing simplified transmission line ter-
minations.
The MCM62110 is available in a 52–pin plastic leaded chip carrier (PLCC).
This device is ideally suited for pipelined systems and systems with multiple
data buses and multiprocessing systems, where a local processor has a bus iso-
lated from a common system bus.
• Single 5 V ± 10% Power Supply
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level
Compatibility
• Fast Access and Cycle Times: 15/17/20 ns Max
• Self–Timed Write Cycles
• Clock Controlled Output Latches
• Address, Chip Enable, and Data Input Registers
• Common Data Inputs and Data Outputs
• Dual I/O for Separate Processor and Memory Buses
• Separate Output Enable Controlled Three–State Outputs
• Odd Parity Checker During Reads
• Open Drain Output on Data Parity Error (DPE) Allowing Wire–ORing of
Outputs
• High Output Drive Capability: 85 pF/Output at Rated Access Time
• High Board Density 52 Lead PLCC Package
• Active High and Low Chip Enables for Easy Memory Depth Expansion
• Can be used as Separate I/O x9
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
E2
E1
PDQ7
SDQ7
VSSQ
PDQ5
SDQ5
VCCQ
PDQ3
SDQ3
VSSQ
PDQ1
SDQ1
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAMES
A0 – A14 . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
E1 . . . . . . . . . . . . . Active Low Chip Enable
E2 . . . . . . . . . . . . . Active High Chip Enable
PIE . . . . . . . . . . . . . Processor Input Enable
SIE . . . . . . . . . . . . . . . System Input Enable
POE . . . . . . . . . . Processor Output Enable
SOE . . . . . . . . . . . . . System Output Enable
DPE . . . . . . . . . . . . . . . . . . Data Parity Error
PDQ0 – PDQ7 . . . . . . . Processor Data I/O
PDQP . . . . . . . . . . . Processor Data Parity
SDQ0 – SDQ7 . . . . . . . . . System Data I/O
SDQP . . . . . . . . . . . . . System Data Parity
VCC . . . . . . . . . . . . . . . + 5 V Power Supply
VCCQ . . . . . . Output Buffer Power Supply
VSSQ . . . . . . . . . . . . Output Buffer Ground
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be
connected for proper operation of the device.
VCC ≥ VCCQ at all times including power up.
PDQP
SDQP
VSSQ
PDQ6
SDQ6
VCCQ
PDQ4
SDQ4
PDQ2
SDQ2
VSSQ
PDQ0
SDQ0
REV 3
5/95
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MCM62110
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