MCM6209C Datasheet, PDF (1/8 Pages) Motorola, Inc – 64K x 4 Bit Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
64K x 4 Bit Fast Static RAM
With Output Enable
The MCM6209C is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in plastic dual–in–line and plastic small–outline J–leaded packages.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• Fast Access Times: 12, 15, 20, 25, and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
• Low Power Operation: 135 – 165 mA Maximum AC
• Fully TTL Compatible — Three–State Output
BLOCK DIAGRAM
A1
VCC
A2
VSS
A3
A4
A6
ROW
DECODER
MEMORY ARRAY
256 ROWS x
64 x 4 COLUMNS
A12
A13
A14
DQ0
INPUT
DQ1
DATA
CONTROL
DQ2
COLUMN I/O
COLUMN DECODER
DQ3
A0 A5 A7 A8 A9 A10 A11 A15
E
W
G
Order this document
by MCM6209C/D
MCM6209C
P PACKAGE
300 MIL PLASTIC
CASE 710B–01
J PACKAGE
300 MIL SOJ
CASE 810B–03
PIN ASSIGNMENT
NC 1
A0 2
A1 3
A2 ₄
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
A9 11
E 12
G 13
VSS ₁₄
28 ^VCC
27 ^A15
26 A14
25 A13
24 A12
23 A11
22 A10
21 NC
20 ^NC
19 DQ0
18 DQ1
17 DQ2
16 DQ3
15 W
PIN NAMES
A0 – A15 . . . . . . . . . . . . . Address Input
DQ0 – DQ3 . . . Data Input/Data Output
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
NC . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . Power Supply (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 3
5/95
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MCM6209C
1