MCM6205D Datasheet, PDF (1/8 Pages) Motorola, Inc – 32K x 9 Bit Fast Static RAM

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
32K x 9 Bit Fast Static RAM
The MCM6205D is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is avail-
able in a plastic small–outline J–leaded package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• Fast Access Times: 15, 20, and 25 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
• Low Power Operation: 130 – 140 mA Maximum AC
• Fully TTL Compatible — Three State Output
BLOCK DIAGRAM
A1
VCC
A3
VSS
A4
A6
MEMORY MATRIX
ROW
256 ROWS x
A7
DECODER
128 x 9 COLUMNS
A9
A10
A11
DQ0
INPUT
COLUMN I/O
DATA
DQ8
CONTROL
COLUMN DECODER
E1
A0 A2 A5 A8 A12 A13 A14
E2
W
G
Order this document
by MCM6205D/D
MCM6205D
J PACKAGE
300 MIL SOJ
CASE 857–02
PIN ASSIGNMENT
NC 1
NC ²
A8 ³
A7 ⁴
A6 ⁵
A5 ⁶
A4 ⁷
A3 ⁸
A2 ⁹
A1 ¹⁰
A0 ¹¹
DQ0 ¹²
DQ1 ¹³
DQ2 ¹⁴
DQ3 ¹⁵
VSS ¹⁶
32 VCC
31 _A14
30 _E2
29 _W
28 _A13
27 _A9
26 _A10
25 _A11
24 G
23 _A12
22 E1
21 _DQ8
20 _DQ7
19 _DQ6
18 _DQ5
17 _DQ4
PIN NAMES
A0 – A14 . . . . . . . . . . . . . Address Input
DQ0 – DQ8 . . . Data Input/Data Output
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E1, E2 . . . . . . . . . . . . . . . . . Chip Enable
NC . . . . . . . . . . . . . . . . . No Connection
VCC . . . . . . . . . . . Power Supply (+ 5 V)
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
REV 1
5/95
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MCM6205D
1