MC74VHC541 Datasheet, PDF (1/6 Pages) Motorola, Inc – Octal Bus Buffer

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal Bus Buffer
The MC74VHC541 is an advanced high speed CMOS octal bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The MC74VHC541 is a noninverting type. When either OE1 or OE2 are
high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 3.7ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 1.2V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
DATA
INPUTS
OUTPUT
ENABLES
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
OE1 ¹
OE2 ¹⁹
LOGIC DIAGRAM
18
Y1
17
Y2
16
Y3
15
Y4
14
Y5
NONINVERTING
OUTPUTS
13
Y6
12
Y7
11
Y8
FUNCTION TABLE
Inputs
OE1 OE2 A
Output Y
L
L
L
L
L
L
H
H
HXX
Z
XHX
Z
MC74VHC541
DW SUFFIX
20–LEAD SOIC WIDE PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
ORDERING INFORMATION
MC74VHCXXXDW SOIC WIDE
MC74VHCXXXDT TSSOP
MC74VHCXXXM
SOIC EIAJ
PIN ASSIGNMENT
OE1 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 VCC
19 OE2
18 Y1
17 Y2
16 Y3
15 Y4
14 Y5
13 Y6
12 Y7
11 Y8
4/98
© Motorola, Inc. 1998
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