MC74VHC157 Datasheet, PDF (1/6 Pages) Motorola, Inc – Quad 2-Channel Multiplexer

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Channel Multiplexer
The MC74VHC157 is an advanced high speed CMOS quad 2–channel
multiplexer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
It consists of four 2–input digital multiplexers with common select (S) and
enable (E) inputs. When E is held High, selection of data is inhibited and all
the outputs go Low.
The select decoding determines whether the A or B inputs get routed to
the corresponding Y outputs.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 4.1ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: VOLP = 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 82 FETs or 20 Equivalent Gates
NIBBLE
INPUTS
E
S
EXPANDED LOGIC DIAGRAM
2
A0
3
B0
4 _Y0
5
A1
6
B1
7
Y1
11
A2
10
B2
9 _Y2
A3 ¹⁴
B3 ¹³
15
1
12 _Y3
DATA
OUTPUTS
MC74VHC157
D SUFFIX
16–LEAD SOIC PACKAGE
CASE 751B–05
DT SUFFIX
16–LEAD TSSOP PACKAGE
CASE 948F–01
M SUFFIX
16–LEAD SOIC EIAJ PACKAGE
CASE 966–01
ORDERING INFORMATION
MC74VHCXXXD
MC74VHCXXXDT
MC74VHCXXXM
SOIC
TSSOP
SOIC EIAJ
PIN ASSIGNMENT
S1
A0 2
B0 3
Y0 4
A1 5
B1 6
Y1 7
GND 8
16 VCC
15 E
14 A3
13 B3
12 Y3
11 A2
10 B2
9 ^Y2
6/97
© Motorola, Inc. 1997
FUNCTION TABLE
Inputs
E
S
Outputs
Y0 – Y3
H
X
L
L
L A0 – A3
L
H B0 – B3
A0 – A3, B0 – B3 = the levels of
the respective Data–Word Inputs.
1
REV 1