MC74LVQ646 Datasheet, PDF (1/10 Pages) Motorola, Inc – LOW-VOLTAGE CMOS OCTAL TRANSCEIVER/ REGISTERED TRANSCEIVER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage Quiet CMOS
Octal Transceiver/Registered
Transceiver
(3-State, Non-Inverting)
The MC74LVQ646 is a high performance, non–inverting octal
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. The MC74LVQ646 is suitable for memory
address driving and all TTL level bus oriented transceiver applications.
Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW–to–HIGH logic level. Output
Enable (OE) and DIR pins are provided to control the transceiver outputs.
In the transceiver mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select controls (SBA,
SAB) can multiplex stored and real–time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when the
enable OE is active LOW. In the isolation mode (OE HIGH), A data may
be stored in the B register or B data may be stored in the A register. Only
one of the two buses, A or B, may be driven at one time.
MC74LVQ646
LVQ
LOW–VOLTAGE CMOS
OCTAL TRANSCEIVER/
REGISTERED TRANSCEIVER
24
1
DW SUFFIX
PLASTIC SOIC
CASE 751E–04
• Designed for 2.7 to 3.6V VCC Operation – Ideal for Low Power/Low
Noise Applications
• Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
• Guaranteed Skew Specifications
• Guaranteed Incident Wave Switching into 75Ω
• Low Static Supply Current (10µA) Substantially Reduces System Power
Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V
24
1
24
1
SD SUFFIX
PLASTIC SSOP
CASE 940D–03
DT SUFFIX
PLASTIC TSSOP
CASE 948H–01
VCC CBA SBA OE B0 B1 B2 B3 B4 B5 B6 B7
24 23 22 21 20 19 18 17 16 15 14 13
Pinout: 24–Lead Package (Top View)
PIN NAMES
Pins
Function
A0–A7
B0–B7
CAB, CBA
SAB, SBA
DIR, OE
Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs
1 2 3 4 5 6 7 8 9 10 11 12
CAB SAB DIR A0 A1 A2 A3 A4 A5 A6 A7 GND
12/95
© Motorola, Inc. 1995
1
REV 0