MC74LCX374 Datasheet, PDF (1/8 Pages) Motorola, Inc – LOW-VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS
Octal D-Type Flip-Flop
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
The MC74LCX374 is a high performance, non–inverting octal D–type
flip–flop operating from a 2.7 to 3.6V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX374 inputs to be
safely driven from 5V devices.
The MC74LCX374 consists of 8 edge–triggered flip–flops with
individual D–type inputs and 3–state true outputs. The buffered clock and
buffered Output Enable (OE) are common to all flip–flops. The eight
flip–flops will store the state of individual D inputs that meet the setup and
hold time requirements on the LOW–to–HIGH Clock (CP) transition. With
the OE LOW, the contents of the eight flip–flops are available at the
outputs. When the OE is HIGH, the outputs go to the high impedance
state. The OE input level does not affect the operation of the flip–flops.
• Designed for 2.7 to 3.6V VCC Operation
• 5V Tolerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0V
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
Pinout: 20–Lead (Top View)
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
MC74LCX374
LOW–VOLTAGE CMOS
OCTAL D–TYPE FLIP–FLOP
20
1
20
1
20
1
20
1
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
PIN NAMES
Pins
Function
OE
CP
D0–D7
O0–O7
Output Enable Input
Clock Pulse Input
Data Inputs
3–State Outputs
11/96
© Motorola, Inc. 1996
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