MC74HCT573A Datasheet, PDF (1/6 Pages) Motorola, Inc – Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting
Transparent Latch with
LSTTL Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT573A is identical in pinout to the LS573. This device may
be used as a level converter for interfacing TTL or NMOS outputs to
High–Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold times becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HCT573A is identical in function to the HCT373A but has the Data
Inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HCT573A is the noninverting version of the HC563A.
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS–Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 10 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 234 FETs or 58.5 Equivalent Gates
— Improved Propagation Delays
— 50% Lower Quiescent Power
LOGIC DIAGRAM
DATA
INPUTS
D0 ²
D1 ³
D2 ⁴
D3 ⁵
D4 ⁶
D5 ⁷
D6 ⁸
D7 ⁹
19 _Q0
18 _Q1
17 _Q2
16 _Q3
15 _Q4
14 _Q5
13 _Q6
12 _Q7
NONINVERTING
OUTPUTS
LATCH ENABLE ¹¹
OUTPUT ENABLE ¹
PIN 20 = VCC
PIN 10 = GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Design Criteria}
Value
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Count*}
58.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Propagation Delay}
1.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Power Dissipation}
5.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Speed Power Product}
0.0075
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{*Equivalent to a two–input NAND gate.}
Units
ea
ns
µW
pJ
10/96
© Motorola, Inc. 1996
1
MC74HCT573A
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
ORDERING INFORMATION
MC74HCTXXXAN Plastic
MC74HCTXXXADW SOIC
MC74HCTXXXADT TSSOP
PIN ASSIGNMENT
OUTPUT
ENABLE
1
D0 2
20 VCC
19 Q0
D1 3
18 Q1
D2 4
17 Q2
D3 5
16 Q3
D4 6
15 Q4
D5 7
14 Q5
D6 8
13 Q6
D7 9
GND 10
12 Q7
11 ^LATCH
ENABLE
FUNCTION TABLE
Inputs
Output Latch
Enable Enable D
Output
Q
L
H
H
H
L
H
L
L
L
L
X No Change
H
X
X
Z
X = Don’t Care
Z = High Impedance
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