MC74HCT273A Datasheet, PDF (1/5 Pages) Motorola, Inc – Octal D Flip-Flop with Common Clock and Reset with LSTTL-Compatible Inputs

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal D Flip-Flop with
Common Clock and Reset
with LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT273A may be used as a level converter for interfacing TTL
or NMOS outputs to High–Speed CMOS inputs.
The HCT273A is identical in pinout to the LS273.
This device consists of eight D flip–flops with common Clock and Reset
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock
input. Reset is asynchronous and active low.
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 284 FETs or 71 Equivalent Gates
LOGIC DIAGRAM
D0 ³
D1 ⁴
DATA
INPUTS
D2 ⁷
D3 ⁸
D4 ¹³
D5 ¹⁴
D6 ¹⁷
D7 ¹⁸
CLOCK ¹¹
2 _Q0
5 _Q1
6 _Q2
9 _Q3
12 _Q4
15 _Q5
16 _Q6
19 _Q7
NONINVERTING
OUTPUTS
RESET ¹
PIN 20 = VCC
PIN 10 = GND
MC74HCT273A
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC74HCTXXXAN Plastic
MC74HCTXXXADW SOIC
PIN ASSIGNMENT
RESET 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CLOCK
FUNCTION TABLE
Inputs
Output
Reset Clock D
Q
L
X
X
L
H
H
H
H
L
L
H
L
X No Change
H
X No Change
X = Don’t Care
Z = High Impedance
2/97
© Motorola, Inc. 1997
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