MC74HC125A Datasheet, PDF (1/6 Pages) ON Semiconductor – Quad 3-State Noninverting Buffers

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 3-State
Noninverting Buffers
High–Performance Silicon–Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to the LS125
and LS126. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used
with 3–state memory address drivers, clock drivers, and other bus–oriented
systems. The devices have four separate output enables that are active–low
(HC125A) or active–high (HC126A).
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
HC125A
Active–Low Output Enables
HC126A
Active–High Output Enables
A1
2
OE1
1
5
A2
OE2
4
3
Y1
A1
2
OE1
1
6
5
Y2
A2
OE2
4
9
A3
OE3
10
12
A4
13
OE4
8 _Y3
A3
9
OE3
10
11
12
Y4
A4
13
OE4
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
HC125A
Inputs Output
A OE Y
HL
H
LL
L
XH
Z
HC126A
Inputs Output
A OE Y
HH H
LH
L
XL
Z
3
Y1
6
Y2
8
Y3
11
Y4
MC74HC125A
MC74HC126A
N SUFFIX
14–LEAD PLASTIC DIP PACKAGE
CASE 646–06
D SUFFIX
14–LEAD PLASTIC SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD PLASTIC TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC74HCXXXAN Plastic
MC74HCXXXAD SOIC
MC74HCXXXADT TSSOP
PIN ASSIGNMENT
OE1 1
A1 2
Y1 3
OE2 4
A2 5
Y2 6
GND 7
14 VCC
13 OE4
12 A4
11 Y4
10 OE3
9 A3
8 Y3
4/97
© Motorola, Inc. 1997
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