MC74HC10A Datasheet, PDF (1/5 Pages) ON Semiconductor – Triple 3-Input NAND Gate High−Performance Silicon−Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Triple 3-Input NAND Gate
High–Performance Silicon–Gate CMOS
The MC74HC10A is identical in pinout to the LS10. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 36 FETs or 9 Equivalent Gates
LOGIC DIAGRAM
1
A1
2
B1
13
C1
3
A2
4
B2
5
C2
9
A3
10
B3
11
C3
12
Y1
6
Y2
Y = ABC
8
Y3
PIN 14 = VCC
PIN 7 = GND
MC74HC10A
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
FUNCTION TABLE
Inputs
Output
A
B
C
Y
L
X
X
H
X
L
X
H
X
X
L
H
H
H
H
L
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
12/97
© Motorola, Inc. 1997
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