MC74AC823 Datasheet, PDF (1/8 Pages) Motorola, Inc – 9-BIT REGISTER WITH 3-STATE OUTPUTS (Non-Inverting)

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9ĆBit Register With 3ĆState
Outputs (NonĆInverting)
The MC74AC/ACT823 consists of nine D-type edge-triggered flip-flops. This
device has 3-state outputs for bus systems, organized in a broadside pinning. In
addition to the clock and output enabled pins, the buffered clock (CP) and buffered
Output Enable (OE) are common to all flip-flips. The flip-flops will store the state of
their individual D inputs that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available
at the outputs. When OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the flip-flops. The
MC74AC/ACT823 has Clear (CLR) and Clock Enable (EN) pins. These devices are
ideal for parity bus interfacing in high performance systems.
When CLR is LOW, and OE is LOW, the outputs are LOW. When CLR is HIGH,
data can be entered into the flip-flops. When EN is LOW, data on the inputs is
transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH,
the outputs do not change state, regardless of the data or clock input transitions.
• 3-State Outputs for Bus Interfacing
• Broad Side Pin Configuration
• ACT has TTL – Compatible Inputs
• High Speed Parallel Positive Edge-Triggered D-Type Flip-Flops
• High Performance Bus Interface Buffering for Busses Carrying Parity
• Outputs Source/Sink 24 mA
Pinout: 24-Lead Packages (Top View)
VCC O0 O1 O2 O3 O4 O5 O6 O7 O8 EN CP
24 23 22 21 20 19 18 17 16 15 14 13
MC74AC823
MC74ACT823
9-BIT REGISTER WITH
3-STATE OUTPUTS
24
1
N SUFFIX
CASE 724-03
PLASTIC PACKAGE
DW SUFFIX
CASE 751E-04
SOIC PACKAGE
PIN NAMES
1 2 3 4 5 6 7 8 9 10 11 12
OE1 D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND
FUNCTION TABLE
D0 – D8
O0 – O8
OE
EN
CLR
CP
Data Inputs
Data Outputs
Output Enable
Clock Enable
Clear
Clock Input
Inputs
OE
CLR
EN
CP
Dn
Internal
Q
Outputs
O
Operating Mode
H
X
L
↑
L
L
H
X
L
↑
H
H
H
L
X
X
X
L
L
L
X
X
X
L
Z
High Z
Z
High Z
Z
Clear
L
Clear
H
H
H
X
X
NC
L
H
H
X
X
NC
Z
Hold
NC
Hold
H
H
L
↑
L
L
H
H
L
↑
H
H
L
H
L
↑
L
L
L
H
L
↑
H
H
Z
Load
Z
Load
L
Load
H
Load
H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; Z = High Impedance State; ↑ = LOW-to-High Transition; NC = No Change
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
FACT DATA
5-1