MC74AC175 Datasheet, PDF (1/6 Pages) ON Semiconductor – QUAD D FLIP-FLOP WITH MASTER RESET

MC74AC175
MC74ACT175
Quad D FlipĆFlop With
Master Reset
The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for
general flip-flop requirements where clock and clear inputs are common. The
information on the D inputs is transferred to storage during the LOW-to-HIGH clock
transition. The device has a Master Reset to simultaneously clear all flip-flops, when
MR is low.
The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual
D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common
to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master
Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock
or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and
Master Reset are common to all storage elements.
• Outputs Source/Sink 24 mA
• ′ACT175 Has TTL Compatible Inputs
QUAD D FLIP-FLOP
WITH MASTER RESET
N SUFFIX
CASE 648-08
PLASTIC
Pinout: 16-Lead Packages (Top View)
VCC Q3 Q3 D3 D2 Q2 Q2 CP
16 15 14 13 12 11 10 9
12345678
MR Q0 Q0 D0 D1 Q1 Q1 GND
PIN NAMES
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
Outputs
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
TRUTH TABLE
Inputs
Outputs
MR
CP
D
Qn
Qn
L
X
X
L
H
H
H
H
L
H
L
L
H
H
L
X
Qn
Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition of Clock
D0 D1 D2 D3
CP
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
FACT DATA
5-1