MC54HC589 Datasheet, PDF (1/10 Pages) Motorola, Inc – 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output High-Performance Silicon-Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
with 3-State Output
High–Performance Silicon–Gate CMOS
The MC54/74HC589 is similar in function to the HC597, which is not a
3–state device. The device inputs are compatible with standard CMOS
outputs, with pullup resistors, they are compatible with LSTTL outputs.
This device consists of an 8–bit storage latch which feeds parallel data to
an 8–bit shift register. Data can also be loaded serially (see Function Table).
The shift register output, QH, is a three–state output, allowing this device to
be used in bus–oriented systems.
The HC589 directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates
MC54/74HC589
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
SERIAL
DATA
INPUT
SA ¹⁴
PARALLEL
DATA
INPUTS
A ¹⁵
B1
C2
D3
E4
F5
G6
H7
LATCH CLOCK ¹²
SHIFT CLOCK ¹¹
SERIAL SHIFT/ 13
PARALLEL LOAD
OUTPUT ENABLE ¹⁰
LOGIC DIAGRAM
DATA
LATCH
SHIFT
REGISTER
VCC = PIN 16
GND = PIN 8
9 _QH
SERIAL
DATA
OUTPUT
PIN ASSIGNMENT
B1
C2
16 VCC
15 A
D3
E4
F5
14 SA
13
SERIAL SHIFT/
PARALLEL LOAD
12 LATCH CLOCK
G6
H7
11 SHIFT CLOCK
10 OUTPUT ENABLE
GND 8
9 QH
10/95
© Motorola, Inc. 1995
3–1
REV 6