MC54HC174A Datasheet, PDF (1/6 Pages) Motorola, Inc – Hex D Flip-Flop With Common Clock And Reset High-Performance Silicon-Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC54/74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of six D flip–flops with common Clock and Reset
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock
input. Reset is asynchronous and active–low.
• Output Drive Capability: 10 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 162 FETs or 40.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 ³
D1 ⁴
D2 ⁶
D3 ¹¹
D4 ¹³
D5 ¹⁴
2 _Q0
5 _Q1
7 _Q2
10 _Q3
12 _Q4
15 _Q5
NONINVERTING
OUTPUTS
CLOCK ⁹
RESET ¹
PIN 16 = VCC
PIN 8 = GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Design Criteria}
Value Units
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Count*}
40.5 ea.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Propagation Delay}
1.5
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Power Dissipation}
5.0
µW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Speed Power Product}
.0075 pJ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{*Equivalent to a two–input NAND gate.}
MC54/74HC174A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
RESET 1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND 8
16 VCC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CLOCK
FUNCTION TABLE
Inputs
Reset Clock
L
X
H
H
H
L
H
Output
D
Q
X
L
H
H
L
L
X No Change
X No Change
10/95
© Motorola, Inc. 1995
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