MC5474HC241A Datasheet, PDF (1/7 Pages) Motorola, Inc – High–Performance Silicon–Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver
High–Performance Silicon–Gate CMOS
The MC54/74HC241A is identical in pinout to the LS241. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed to be
used with 3–state memory address drivers, clock drivers, and other
sub–oriented systems. The device has noninverted outputs and two output
enables. Enable A is active–low and Enable B is active–high.
The HC241A is similar in function to the HC244A and HC240A.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
A1 ²
A2 ⁴
A3 ⁶
DATA
INPUTS
A4 ⁸
B1 ¹¹
B2 ¹³
B3 ¹⁵
B4 ¹⁷
OUTPUT ENABLE A ¹
ENABLES _{ENABLE B} ¹⁹
LOGIC DIAGRAM
18 _YA1
16 _YA2
14 _YA3
12 _YA4
NONINVERTING
9 _YB1 ^OUTPUTS
7 _YB2
5 _YB3
3 _YB4
PIN 20 = VCC
PIN 10 = GND
MC54/74HC241A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
ENABLE A 1
A1 2
YB4 3
A2 4
YB3 5
A3 6
YB2 7
A4 8
YB1 9
GND 10
20 VCC
19 ENABLE B
18 YA1
17 B4
16 YA2
15 B3
14 YA3
13 B2
12 YA4
11 B1
FUNCTION TABLE
Inputs
Enable
AA
LL
LH
HX
Output Inputs
Enable
YA
BB
L
HL
H
HH
Z
LX
Output
YB
L
H
Z
Z = high impedance
10/95
© Motorola, Inc. 1995
1
REV 6