|
MC5474HC175A Datasheet, PDF (1/8 Pages) Motorola, Inc – High–Performance Silicon–Gate CMOS | |||
|
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
Quad D Flip-Flop with
Common Clock and Reset
HighâPerformance SiliconâGate CMOS
The MC54/74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of four D flipâflops with common Reset and Clock
inputs, and separate D inputs. Reset (activeâlow) is asynchronous and
occurs when a low level is applied to the Reset input. Information at a D input
is transferred to the corresponding Q output on the next positive going edge
of the Clock input.
⢠Output Drive Capability: 10 LSTTL Loads
⢠Outputs Directly Interface to CMOS, NMOS, and TTL
⢠Operating Voltage Range: 2 to 6 V
⢠Low Input Current: 1 µA
⢠High Noise Immunity Characteristic of CMOS Devices
⢠In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
⢠Chip Complexity 166 FETs or 41.5 Equivalent Gates
LOGIC DIAGRAM
CLOCK 9
DATA
INPUTS
D0 4
D1 5
D2 12
D3 13
RESET 1
PIN 16 = VCC
PIN 8 = GND
2 Q0
3 Q0
7 Q1
6 Q1
10 Q2
11 Q2
15 Q3
14 Q3
INVERTING
AND
NONINVERTING
OUTPUTS
MC54/74HC175A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620â10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648â08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751Bâ05
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948Fâ01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
RESET 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CLOCK
This document contains information on a product under development. Motorola reserves the right to
change or discontinue this product without notice.
FUNCTION TABLE
Inputs
Reset Clock D
Outputs
QQ
L
XXLH
H
HH L
H
L LH
H
L X No Change
10/95
© Motorola, Inc. 1995
1
REV 0
|
▷ |