MC5474HC175 Datasheet, PDF (1/7 Pages) Motorola, Inc – High–Performance Silicon–Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC54/74HC175 is identical in pinout to the LS175. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of four D flip–flops with common Reset and Clock
inputs, and separate D inputs. Reset (active–low) is asynchronous and
occurs when a low level is applied to the Reset input. Information at a D input
is transferred to the corresponding Q output on the next positive going edge
of the Clock input.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity 166 FETs or 41.5 Equivalent Gates
LOGIC DIAGRAM
CLOCK ⁹
DATA
INPUTS
D0 ⁴
D1 ⁵
D2 ¹²
D3 ¹³
RESET ¹
PIN 16 = VCC
PIN 8 = GND
2 _Q0
3 _Q0
7 _Q1
6 _Q1
10 _Q2
11 _Q2
15 _Q3
14 _Q3
INVERTING
AND
NONINVERTING
OUTPUTS
MC54/74HC175
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
RESET 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CLOCK
FUNCTION TABLE
Inputs
Reset Clock D
Outputs
QQ
L
XXLH
H
HH L
H
L LH
H
L X No Change
10/95
© Motorola, Inc. 1995
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