MC5474F74 Datasheet, PDF (1/3 Pages) Motorola, Inc – DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The MC54/74F74 is a dual D-type flip-flop with Direct Clear and Set inputs
and complementary (Q, Q) outputs. Information at the input is transferred to
the outputs on the positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
• ESD ^> 4000 Volts
CONNECTION DIAGRAM
VCC CD2 D2 CP2 SD2 Q2 Q2
14 13 12 11 10 9 8
D1 ^CD1 Q1
CP1 SD1 Q1
CP2 ^SD2 Q2
D2 CD2 Q2
1234567
CD1 D1 CP1 SD1 Q1 Q1 GND
FUNCTION TABLE (Each Half)
Input
Outputs
@ tn
D
@ tn + 1
QQ
L
LH
H
HL
Asynchronous Inputs:
LOW Input to SD sets Q to HIGH level
LOW Input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse
MC54/74F74
DUAL D-TYPE POSITIVE
EDGE-TRIGGERED FLIP-FLOP
FAST™ SCHOTTKY TTL
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
MC54FXXJ
MC74FXXN
MC74FXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
4
10
2
D1SD1Q1
5 12 D2SD2Q2
9
3 CP1
11 CP2
Q1
CD1
6
Q2
CD2
8
1
13
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
4-33