MC54-74HCT574A Datasheet, PDF (1/6 Pages) Motorola, Inc – High–Performance Silicon–Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State
Noninverting D Flip-Flop with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC54/74HCT574A is identical in pinout to the LS574. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states of
the flip–flops, but when Output Enable is high, all device outputs are
forced to the high–impedance state. Thus, data may be stored even when
the outputs are not enabled.
The HCT574A is identical in function to the HCT374A but has the
flip–flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
• Output Drive Capability: 15 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 ²
D1 ³
D2 ⁴
D3 ⁵
D4 ⁶
D5 ⁷
D6 ⁸
D7 ⁹
19 _Q0
18 _Q1
17 _Q2
16 _Q3
15 _Q4
14 _Q5
13 _Q6
12 _Q7
NON–
INVERTING
OUTPUTS
CLOCK ¹¹
OUTPUT ENABLE ¹
PIN 20 = VCC
PIN 10 = GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Design Criteria}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Count*}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Propagation Delay}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Power Dissipation}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Speed Power Product}
Value Units
71.5
ea
1.5
ns
5.0
µW
0.0075 pJ
* Equivalent to a two–input NAND gate.
MC54/74HCT574A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCTXXXAJ Ceramic
MC74HCTXXXAN Plastic
MC74HCTXXXADW SOIC
PIN ASSIGNMENT
OUTPUT ₁
ENABLE
D0 2
D1 3
20 VCC
19 Q0
18 Q1
D2 4
17 Q2
D3 5
D4 6
D5 7
16 Q3
15 Q4
14 Q5
D6 8
13 Q6
D7 9
GND 10
12 Q7
11 CLOCK
FUNCTION TABLE
Inputs
Output
OE Clock D
Q
L
L
L
L,H,
H
X
H
H
L
L
X No Change
X
Z
X = don’t care
Z = high impedance
3/97
© Motorola, Inc. 1997
3–1
REV 7