MC54-74HC640A Datasheet, PDF (1/7 Pages) Motorola, Inc – High–Performance Silicon–Gate CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Inverting
Bus Transceiver
High–Performance Silicon–Gate CMOS
The MC54/74HC640A is identical in pinout to the LS640. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC640A is a 3–state transceiver that is used for 2–way asynchronous
communication between data buses. The device has an active–low Output
Enable pin, which is used to place the I/O ports into high–impedance states.
The Direction control determines whether data flows from A to B or from B
to A.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 276 FETs or 69 Equivalent Gates
MC54/74HC640A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
A
DATA
PORT
A1 ²
A2 ³
A3 ⁴
A4 ⁵
A5 ⁶
A6 ⁷
A7 ⁸
A8 ⁹
DIRECTION ¹
OUTPUT ENABLE ¹⁹
LOGIC DIAGRAM
PIN 10 = GND
PIN 20 = VCC
18 _B1
17 _B2
16 _B3
15 _B4
14 _B5
13 _B6
12 _B7
11 _B8
B
DATA
PORT
PIN ASSIGNMENT
DIRECTION 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
GND 10
20 VCC
19
OUTPUT
ENABLE
18 B1
17 B2
16 B3
15 B4
14 B5
13 B6
12 B7
11 B8
FUNCTION TABLE
Control Inputs
Output
Enable Direction
Operation
L
L
Data Transmitted from Bus B
to Bus A (Inverted)
L
H
Data Transmitted from Bus A
to Bus B (Inverted)
H
X
Buses Isolated
(High–Impedance State)
X = don’t care
2/97
© Motorola, Inc. 1997
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