MC54-74HC373A Datasheet, PDF (1/8 Pages) Motorola, Inc – Octal 3-State Non-Inverting Transparent Latch

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Non-Inverting
Transparent Latch
High–Performance Silicon–Gate CMOS
The MC54/74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but when
Output Enable is high, all device outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not enabled.
The HC373A is identical in function to the HC573A which has the data
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC373A is the non–inverting version of the HC533A.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 186 FETs or 46.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 ³
D1 ⁴
D2 ⁷
D3 ⁸
D4 ¹³
D5 ¹⁴
D6 ¹⁷
D7 ¹⁸
2 _Q0
5 _Q1
6 _Q2
9 _Q3
12 _Q4
15 _Q5
16 _Q6
19 _Q7
NONINVERTING
OUTPUTS
LATCH ENABLE ¹¹
OUTPUT ENABLE ¹
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Design Criteria}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Count*}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Internal Gate Propagation Delay
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Power Dissipation}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Speed Power Product}
PIN 20 = VCC
PIN 10 = GND
Value
46.5
1.5
5.0
0.0075
Units
ea
ns
µW
pJ
* Equivalent to a two–input NAND gate.
MC54/74HC373A
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
20
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
ORDERING INFORMATION
MC54HCXXXAJ
Ceramic
MC74HCXXXAN
Plastic
MC74HCXXXADW SOIC
MC74HCXXXASD SSOP
MC74HCXXXADT
TSSOP
PIN ASSIGNMENT
OUTPUT ₁
ENABLE
Q0 2
20 VCC
19 Q7
D0 3
18 D7
D1 4
17 D6
Q1 5
16 Q6
Q2 6
15 Q5
D2 7
14 D5
D3 8
13 D4
Q3 9
GND 10
12 Q4
11 ^LATCH
ENABLE
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable D
Q
L
H
H
H
L
H
L
L
L
L
X No Change
H
X
X
Z
X = Don’t Care
Z = High Impedance
3/97
© Motorola, Inc. 1997
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