MC54-74HC354 Datasheet, PDF (1/9 Pages) Motorola, Inc – 8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Input Data Selector/
Multiplexer With Data and
Address Latches and
3-State Outputs
High–Performance Silicon–Gate CMOS
The MC54/74HC354 is identical in pinout to the LS354. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC354 selects one of eight latched binary Data Inputs, as deter-
mined by the Address Inputs. The information at the Data Inputs is stored
in the transparent 8–bit Data Latch when the Data–Latch Enable pin is
held high. The Address information may be stored in the transparent
Address Latch, which is enabled by the active–high Address–Enable pin.
The device outputs are placed in high–impedance states when Output
Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.
The HC354 has a clocked Data Latch that is not transparent.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2 to 6V
• Low Input Current: 1µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 326 FETs or 81.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
8
D0
7
D1
6
D2
5
D3
4
D4
3
D5
2
D6
1
D7
8–BIT
DATA
LATCH
(TRANS–
PARENT)
8–BIT
MULTI–
PLEXER
3–STATE
OUTPUT
CONTROL
19
Y
18
Y
3–STATE
DATA
OUTPUTS
DATA–LATCH ⁹
ENABLE
ADDRESS
INPUTS
14
A0
13
A1
12
A2
ADDRESS–LATCH ¹¹
ENABLE
OUTPUT
ENABLES
15
OE1
16
OE2
17
OE3
ADDRESS
LATCH
(TRANS–
PARENT)
PIN 20 = VCC
PIN 10 = GND
10/95
© Motorola, Inc. 1995
1
MC54/74HC354
20
1
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW
Ceramic
Plastic
SOIC
Pinout: 20–Lead Package (Top View)
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
D0 8
Data–Latch ₉
Enable
GND 10
20 VCC
19 Y
18 Y
17 OE3
16 OE2
15 OE1
14 A0
13 A1
12 A2
11
Address–Latch
Enable
REV 7