MC54-74HC259A Datasheet, PDF (1/8 Pages) Motorola, Inc – 8-Bit Addressable Latch 1-of-8 Decoder

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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8-Bit Addressable Latch
1-of-8 Decoder
High–Performance Silicon–Gate CMOS
The MC54/74HC259A is identical in pinout to the LS259. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC259A has four modes of operation as shown in the mode selection
table. In the addressable latch mode, the data on Data In is written into the
addressed latch. The addressed latch follows the data input with all
non–addressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous state and are unaffected by the
Data or Address inputs. In the one–of–eight decoding or demultiplexing
mode, the addressed output follows the state of Data In with all other outputs
in the LOW state. In the Reset mode all outputs are LOW and unaffected by
the address and data inputs. When operating the HC259A as an
addressable latch, changing more than one bit of the address could impose
a transient wrong address. Therefore, this should only be done while in the
memory mode.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 202 FETs or 50.5 Equivalent Gates
LOGIC DIAGRAM
ADDRESS
INPUTS
A0 ¹
A1 ²
A2 ³
DATA IN ¹³
RESET ¹⁵
ENABLE ¹⁴
4 _Q0
5 _Q1
6 _Q2
7 _Q3
9 _Q4
10 _Q5
11 _Q6
12 _Q7
NONINVERTING
OUTPUTS
PIN 16 = VCC
PIN 8 = GND
MC54/74HC259A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
16
1
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
SOIC PACKAGE
CASE 751B–05
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
A0 1
A1 2
16 VCC
15 RESET
A2 3
14 ENABLE
Q0 4
Q1 5
13 DATA IN
12 Q7
Q2 6
Q3 ⁷
GND 8
11 Q6
10 Q5
9 Q4
MODE SELECTION TABLE
Enable
L
H
L
H
Reset
H
H
L
L
Mode
Addressable Latch
Memory
8–Line Demultiplexer
Reset
LATCH SELECTION TABLE
Address Inputs
C
B
A
Latch
Addressed
L
L
L
Q0
L
L
H
Q1
L
H
L
Q2
L
H
H
Q3
H
L
L
Q4
H
L
H
Q5
H
H
L
Q6
H
H
H
Q7
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
© Motorola, Inc. 1995
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