MC54-74HC165A Datasheet, PDF (1/9 Pages) Motorola, Inc – 8-BIT SERIAL OR PARALLEL-INPUT/SERIAL-OUTPUT SHIFT REGISTER

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High–Performance Silicon–Gate CMOS
The MC54/74HC165A is identical in pinout to the LS165. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device is an 8–bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).
The 2–input NOR clock may be used either by combining two independent
clock sources or by designating one of the clock inputs to act as a clock
inhibit.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates
LOGIC DIAGRAM
MC54/74HC165A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
16
1
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
SOIC PACKAGE
CASE 751B–05
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
PARALLEL
DATA
INPUTS
A ¹¹
B ¹²
13
C
D ¹⁴
E3
F4
G5
SERIAL
DATA
INPUT
H6
SA ¹⁰
SERIAL SHIFT/ 1
PARALLEL LOAD
CLOCK ²
CLOCK INHIBIT ¹⁵
9 _QH
7
QH
SERIAL
DATA
OUTPUTS
PIN 16 = VCC
PIN 8 = GND
PIN ASSIGNMENT
SERIAL SHIFT/
PARALLEL LOAD
1
CLOCK 2
16 VCC
15 CLOCK INHIBIT
E3
14 D
F4
13 C
G5
12 B
H6
11 A
QH 7
GND 8
10 SA
9 QH
FUNCTION TABLE
Inputs
Serial Shift/
Clock
Parallel Load Clock Inhibit SA
L
X
X
X
H
L
L
H
L
H
H
L
L
H
L
H
H
X
H
X
H
H
X
X
Internal Stages Output
A–H
a…h
X
X
X
X
X
X
QA
QB
QH
a
b
h
L
QAn QGn
H
QAn QGn
L
QAn QGn
H
QAn QGn
No Change
Operation
Asynchronous Parallel Load
Serial Shift via Clock
Serial Shift via Clock Inhibit
Inhibited Clock
H
L
L
X
X
No Change
No Clock
X = don’t care
QAn – QGn = Data shifted from the preceding stage
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
10/95
© Motorola, Inc. 1995
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