MC44460 Datasheet, PDF (1/16 Pages) Motorola, Inc – PICTURE–IN–PICTURE (PIP) CONTROLLER

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Advance Information
Picture-in-Picture
(PIP) Controller
The MC44460 Picture–in–Picture (PIP) controller is a low cost member of
a family of high performance PIP controllers and video signal processors for
television. It is NTSC compatible and contains all the analog signal
processing, control logic and memory necessary to provide for the overlay of
a small picture from a second non synchronized source onto the main picture
of a television. All control and setup of the MC44460 is via a standard two pin
I2C bus interface. The device is fabricated using BICMOS technology. It is
available in a 56–pin shrink dip (SDIP) package.
The main features of the MC44460 are:
• Two NTSC CVBS Inputs
• Switchable Main and PIP Video Signals
• Single NTSC CVBS Output Allows Simple TV Chassis Integration
• Two PIP Sizes; 1/16 and 1/9 Screen Area
• Freeze Field Feature
• Variable PIP Position in 64–X by 64–Y Steps
• PIP Border with Programmable Color
• Programmable PIP Tint and Saturation Control
• Automatic Main to PIP Contrast Balance
• Vertical Filter
• Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI
• Minimal RFI Allows Simple Low Cost Application into TV
• I2C Bus Control – No External Variable Adjustments Needed
• Operates from a Single 5.0 V Supply
• Economical 56–Pin Shrink DIP Package
MC44460
PICTURE–IN–PICTURE
(PIP) CONTROLLER
SEMICONDUCTOR
TECHNICAL DATA
56
1
B SUFFIX
PLASTIC PACKAGE
CASE 859
(SDIP)
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC44460B TJ = –65° to +150°C
SDIP
Sync Out
28
Representative Block Diagram
Decoder Clamp Caps
Filter PLL
ADC Mid–Ref
33 40 41 42 51
Video 1 ³⁶
Video 2 ³⁴
37
Decoder ACC
49
Main Out
Decoder Xtal ³⁸
39
Decoder PLL
7
16 FSC PLL
44
Encoder Phase ₄₅
Encoder ACC
Input
Switch
PIP
Switch
Low Pass
Filter
Band Pass
Filter
NTSC
Decoder
Filter
Tracking
Y
Y
YUV
V Clamp V
U
U
0°
90° ^{57.28 MHz}
4X S/C
Osc + PLL
14.32 MHz
NTSC
Encoder
16X S/C
Osc + PLL
3.0 MHz
LPF
0°
90°
4X S/C
Osc + PLL
Clamp
YUV
3.0 MHz
LPF
3.0 MHz
LPF
H and V
Timebase
29 _{Sync In}
31 _{H PLL}
32 _{503 kHz Res}
6–Bit
ADC ₆
3
Tint DAC
Sat DAC
U DAC
6
Vert
6
6
Digital
Logic
1
2
3
Hin
Vin
SCL
4 _SDA
5 _Reset
10 _{Vid 1/2 Sel}
30 _{Multi Test}
V DAC
Y DAC
6
Memory
I Ref
8.0 k x 8
6
DRAM
46 47
52 53 54
6
Encoder
PLL
Encoder
Xtal
Encoder Clamp Caps
This device contains 500,000 active transistors.
Cur Ref
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
1