MC1670 Datasheet, PDF (1/4 Pages) Motorola, Inc – Master-Slave Flip-Flop

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Master-Slave Flip-Flop
Master slave construction renders the MC1670 relatively insensitive to the
shape of the clock waveform, since only the voltage levels at the clock inputs
control the transfer of information from data input (D) to output.
When both clock inputs (C1 and C2) are in the low state, the data input
affects only the “Master” portion of the flip-flop. The data present in the “Master”
is transferred to the “Slave” when clock inputs (C1 “OR” C2) are taken from a
low to a high level. In other words, the output state of the flip-flop changes on the
positive transition of the clock pulse.
While either C1 “OR” C2 is in the high state, the “Master” (and data input) is
disabled.
Asynchronous Set (S) and Reset (R) override Clock (C) and Data (D) inputs.
Power Dissipation = 220 mW typ (No Load)
fTog = 350 MHz typ
TRUTH TABLE
R
S
D
C
L
H
X
X
H
L
X
X
H
H
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
H
H
ND = Not Defined
C = C1 + C2
Qn+1
H
L
N.D.
Qn
L
Qn
Qn
H
Qn
ELECTRICAL CHARACTERISTICS
–30°C
Characteristic
Symbol Min Max
Power Supply Drain Current IE
Input Current
IinH
Set, Reset
Clock
Data
——
——
——
——
Switching Times
Propagation Delay
Rise Time (10% to 90%)
Fall Time (10% to 90%)
tpd 1.0 2.7
t+
0.9 2.7
t–
0.5 2.1
Setup Time
Hold Time
Toggle Frequency
tS“1” — —
tS“0” — —
tH“1” — —
tH“0” — —
fTog 270 —
+ 25°C
Min Max
— 48
— 550
— 250
— 270
1.1 2.5
1.0 2.5
0.6 1.9
0.4 —
0.5 —
0.3 —
0.5 —
300 —
+ 85°C
Min Max
——
——
——
——
1.1 2.9
Unit
mAdc
µAdc
ns
1.0 2.9 ns
0.6 2.3 ns
— — ns
——
— — ns
——
270 — MHz
MC1670
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
LOGIC DIAGRAM
5S
7 C1
Q2
9 C2
11 D
4R
Q3
VCC1 = Pin 1
VCC2 = Pin 16
VEE = Pin 8
PIN ASSIGNMENT
VCC1 1
Q2
Q3
RESET 4
SET 5
NC 6
CLOCK 1 7
VEE 8
16 VCC2
15 NC
14 NC
13 NC
12 NC
11 DATA
10 NC
9 CLOCK 2
3/93
© Motorola, Inc. 1996
4–356
REV 5