MC14583B Datasheet, PDF (1/8 Pages) Motorola, Inc – Dual Schmitt Trigger

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Schmitt Trigger
The MC14583B is a dual Schmitt trigger constructed with complementary
P–channel and N–channel MOS devices on a monolithic silicon substrate.
Each Schmitt trigger is functionally independent except for a common
3–state input and an internally–connected Exclusive OR output for use in
line receiver applications. Trigger levels are adjustable through the positive,
negative, and common terminals with the use of external resistors.
Applications include the speed–up of a slow waveform edge in interface
receivers, level detectors, etc.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Single Supply Operation
• Capable of Driving Two Low–power TTL Loads or One Low–power
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{• Resistor Adjustable Trigger Levels}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
± 10
mA
per Pin
PD Power Dissipation, per Package†
500
mW
Tstg Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC DIAGRAM
POSITIVE A NEGATIVE A
65
7 COMMON A
Ain 9
4 Aout
3–STATE
OUTPUT DISABLE
13
11 Aout
14 EXCLUSIVE OR
Bin 15
1 COMMON B
23
POSITIVE B2 NEGATIVE B
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
10 Bout
12 Bout
VDD = PIN 16
VSS = PIN 8
MC14583B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
6 57
VDD = PIN 16
VSS = PIN 8
APos ANeg ACom
9
Ain
Aout
4
Aout
11
13
Dis
14
15
Bin
Bout
10
Bout
12
BPos BNeg BCom
2 31
TRUTH TABLE
Inputs
Outputs
ę A B Dis Aout Aout Bout Bout
00 0 0 Z 0 Z 0
00 1 0
1
0
10
01 0 0 Z 1 Z 1
01 1 0
1
1
01
10 0 1 Z 0 Z 1
10 1 1
0
0
11
11 0 1 Z 1 Z 0
11 1 1
0
1
00
Z = High impedance at output
MC14583B
1