MC14568B Datasheet, PDF (1/12 Pages) Motorola, Inc – Phase Comparator and Programmable Counters

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Phase Comparator and
Programmable Counters
The MC14568B consists of a phase comparator, a divide–by–4, 16, 64 or
100 counter and a programmable divide–by–N 4–bit binary counter (all
positive–edge triggered) constructed with MOS P–channel and N–channel
enhancement mode devices (complementary MOS) in a monolithic structure.
The MC14568B has been designed for use in conjunction with a
programmable divide–by–N counter for frequency synthesizers and phase–
locked loop applications requiring low power dissipation and/or high noise
immunity.
This device can be used with both counters cascaded and the output of
the second counter connected to the phase comparator (CTL high), or used
independently of the programmable divide–by–N counter, for example
cascaded with a MC14569B, MC14522B or MC14526B (CTL low).
• Supply Voltage Range = 3.0 to 18 V
• Capable of Driving Two Low–Power TTL Loads, One Low–Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• Chip Complexity: 549 FETs or 137 Equivalent Gates}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages referenced to VSS)}
Rating
Symbol
Value
Unit
DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
Power Dissipation, per Package†
Operating Temperature Range
Storage Temperature Range
VDD
Vin
Iin
PD
TA
Tstg
– 0.5 to + 18
Vdc
– 0.5 to VDD + 0.5 Vdc
± 10
mAdc
500
mW
– 55 to + 125
_C
– 65 to + 150
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
MC14568B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
TRUTH TABLE
F
Pin 10
0
0
1
1
G
Pin 11
0
1
0
1
Division Ratio
of Counter D1
4
16
64
100
The divide by zero state on the pro-
grammable divide–by–N 4–bit binary
counter, D2, is illegal.
PCin 14
(REF.)
A _PHASE
B ^COMPARATOR
13 PCout
12 LD
TG
TG
C1 9
CTL 15
“0” 3
PE 2
COUNTER D1
TG
4–BIT
PROGRAMMABLE
COUNTER D2
VDD = PIN 16
VSS = PIN 8
DP3
DP0
4 567
DP2 DP1
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
11 G
PCin
10 F
C1
1 Q1/C2
“0”
CTL HIGH
P/C
PCout PCin
LD
D1
C1
D2
“0”
Q1/C2
CTL LOW
PCout
P/C
LD
D1
D2
Q1/C2
MC14568B
1