MC14553B Datasheet, PDF (1/8 Pages) Motorola, Inc – 3-Digit BCD Counter

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14553B
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered
BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
• TTL Compatible Outputs
• On–Chip Oscillator
• Cascadable
• Clock Disable Input
• Pulse Shaping Permits Very Slow Rise Times on Input Clock
• Output Latches
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• Master Reset}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Symbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin
Input Current (DC or Transient), per Pin
± 10
mA
Iout Output Current (DC or Transient), per Pin
+ 20
mA
PD Power Dissipation, per Package†
500
mW
Tstg Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TRUTH TABLE
Inputs
Master
Reset Clock Disable
LE
0
0
0
0
0
0
0
X
1
X
0
1
0
0
1
0
0
0
X
X
0
X
X
0
X
X
1
1
X
X
0
X = Don’t Care
Outputs
No Change
Advance
No Change
Advance
No Change
No Change
Latched
Latched
Q0 = Q1 = Q2 = Q3 = 0
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
4
3
CIA CIB Q0
9
12
CLOCK
Q1
7
10
LE
Q2
6
Q3
5
11
DIS
O.F.
14
DS1
2
13
MR
DS2
1
DS3
15
VDD = PIN 16
VSS = PIN 8
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v v ^{operation, Vin and Vout should be constrained}
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14553B
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