MC14522B Datasheet, PDF (1/10 Pages) Motorola, Inc – Presettable 4-Bit Down Counters

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Presettable 4-Bit Down Counters
The MC14522B BCD counter and the MC14526B binary counter are
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
These devices are presettable, cascadable, synchronous down counters
with a decoded “0” state output for divide–by–N applications. In single stage
applications the “0” output is applied to the Preset Enable input. The
Cascade Feedback input allows cascade divide–by–N operation with no
additional gates required. The Inhibit input allows disabling of the pulse
counting function. Inhibit may also be used as a negative edge clock.
These complementary MOS counters can be used in frequency synthesiz-
ers, phase–locked loops, and other frequency division applications requiring
low power dissipation and/or high noise immunity.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Design — Incremented on Positive Transition of
Clock or Negative Transition of Inhibit
• Asynchronous Preset Enable
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• Capable of Driving Two Low–power TTL Loads or One Low–power}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Schottky TTL Load Over the Rated Temperature Range}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^Symbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0
V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
± 10
mA
per Pin
PD Power Dissipation, per Package†
500
mW
Tstg Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
FUNCTION TABLE
Inputs
Output
Preset Cascade
Clock Reset Inhibit Enable Feedback “0”
Resulting
Function
X
H
X
L
L
L Asynchronous reset*
X
H
X
H
L
H Asynchronous reset
X
H
X
X
H
H Asynchronous reset
X
L
X
H
X
L Asynchronous preset
L
H
L
X
L Decrement inhibited
L
L
L
X
L Decrement inhibited
L
L
L
L
L No change** (inactive edge)
H
L
L
L
L No change** (inactive edge)
L
L
L
L
L Decrement**
H
L
L
L
L Decrement**
X = Don’t Care
NOTES:
* Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.
MC14522B
MC14526B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
Q3 1
P3 2
PE 3
INHIBIT 4
P0 5
CLOCK 6
Q0 7
VSS 8
16 VDD
15 Q2
14 P2
13 CF
12 “0”
11 P1
10 RESET
9 Q1
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v v ^{operation, Vin and Vout should be constrained}
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14522B MC14526B
1