MC14508B Datasheet, PDF (1/7 Pages) Motorola, Inc – Dual 4-Bit Latch

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 4-Bit Latch
The MC14508B dual 4–bit latch is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure. The
part consists of two identical, independent 4–bit latches with separate Strobe
(ST) and Master Reset (MR) controls. Separate Disable inputs force the
outputs to a high impedance state and allow the devices to be used in time
sharing bus line applications.
These complementary MOS latches find primary use in buffer storage,
holding register, or general digital logic functions where low power
dissipation and/or high noise immunity is desired.
• 3–State Output
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ • Capable–of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
Symbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
± 10
mA
per Pin
PD Power Dissipation, per Package†
Tstg Storage Temperature
500
mW
– 65 to + 150 _C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TRUTH TABLE
MR ST Disable D3 D2 D1 D0 Q3 Q2 Q1 Q0
01
0
00000000
01
0
00010001
01
0
00100010
01
0
01000100
01
0
10001000
00
0
XXXX
Latched
1X
0
XXXX0 0 0 0
XX
1
XXXX
High Impedance
X = Don’t Care
DIS
CIRCUIT DIAGRAM
VDD
MR
ST
Dn
Qn
MC14508B
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
1
MR _Q0
5
2
ST
3
DIS Q1
7
4
D0
6
D1 ^Q2
9
8
10
D2
D3
Q3
11
13
MR _Q0
17
14
ST
15
DIS Q1
19
16
D0
18
D1 ^Q2
21
20
22
D2
D3
Q3
23
VDD = PIN 24
VSS = PIN 12
(TO OTHER THREE LATCHES)
REV 3
1/94
©_MM_Cot₁or₄o₅la₀, I₈n_Bc. 1995
344
VSS
MOTOROLA CMOS LOGIC DATA