MC14506UB Datasheet, PDF (1/7 Pages) Motorola, Inc – Dual 2-wide, 2-input Expandable And-Or-Invert Gate

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14506UB
Dual 2-Wide, 2-Input
Expandable AND-OR-INVERT
Gate
The MC14506UB is an expandable AND–OR–INVERT gate with inhibit
and 3–state output. The expand option allows cascading with any other gate,
which may be carried as far as desired as long as the propagation delay
added with each gate is considered. For example, the second AOI gate in
this device may be used to expand the first gate, giving an expanded 4–wide,
2–input AOI gate. This device is useful in data control and digital multiplexing
applications.
• 3–State Output
• Separate Inhibit Line
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ • Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
Symbol
Parameter
Value
Unit
VDD DC Supply Voltage
– 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
± 10
mA
per Pin
PD Power Dissipation, per Package†
500
mW
Tstg Storage Temperature
– 65 to + 150 _C
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC DIAGRAM
AA 1
BA 2
CA 3
DA 4
EA 5
INH 6
DIS 14
EB 13
DB 12
CB 11
BB 10
AB 9
3–STATE
OUTPUT DISABLE
15 ZA
VDD = PIN 16
VSS = PIN 8
7 ZB
Z = (AB + CD + E + I)
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v v ^{operation, Vin and Vout should be constrained}
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
TRUTH TABLE
A B C D E Inhibit Disable
Z
00001 0
0X0X1 0
0XX0 1 0
X00X1 0
X0X01 0
1 1XXX X
XX1 1X X
XXXX0 X
XXXXX 1
XXXXX X
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
High
Impedance
X = Don’t Care
REV 3
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©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14506UB
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