MC14503B Datasheet, PDF (1/6 Pages) ON Semiconductor – Hex Non-Inverting 3-State Buffer

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Non-Inverting 3-State
Buffer
The MC14503B is a hex non–inverting buffer with 3–state outputs, and a
high current source and sink capability. The 3–state outputs make it useful in
common bussing applications. Two disable controls are provided. A high
level on the Disable A input causes the outputs of buffers 1 through 4 to go
into a high impedance state and a high level on the Disable B input causes
the outputs of buffers 5 and 6 to go into a high impedance state.
• 3–State Outputs
• TTL Compatible — Will Drive One TTL Load Over Full Temperature
Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• Two Disable Controls for Added Versatility}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• Pin for Pin Replacement for MM80C97 and 340097}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VDD DC Supply Voltage}
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Iin
Input Current (DC or Transient), per Pin
± 10
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Iout Output Current (DC or Transient), per Pin
± 25
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation, per Package†
500
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Tstg Storage Temperature}
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^TL
Lead Temperature (8–Second Soldering)
260
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{* Maximum Ratings are those values beyond which damage to the device may occur.}
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CIRCUIT DIAGRAM
ONE OF TWO/FOUR BUFFERS
VDD
* INn
OUTn
* DISABLE
* INPUT
VSS
TO OTHER BUFFERS
* Diode protection on all inputs (not shown)
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14503B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
TRUTH TABLE
Appropriate
Disable
Inn
Input
Outn
0
0
0
1
0
1
X
1
High
Impedance
X = Don’t Care
LOGIC DIAGRAM
DISABLE B ¹⁵
IN 5 ¹²
IN 6 ¹⁴
IN 1 ²
IN 2 ⁴
IN 3 ⁶
IN 4 ¹⁰
DISABLE A ¹
11 _{OUT 5}
13 _{OUT 6}
3 _{OUT 1}
5 _{OUT 2}
7 _{OUT 3}
9 _{OUT 4}
VDD = PIN 16
VSS = PIN 8
REV 3
1/94
©_MM_Cot₁or₄o₅la₀, I₃n_Bc. 1995
326
MOTOROLA CMOS LOGIC DATA