MC14501UB Datasheet, PDF (1/6 Pages) Motorola, Inc – Dual 4–Input “NAND” Gate 2–Input “NOR/OR” Gate 8–Input “AND/NAND” Gate

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple Gate
Dual 4–Input “NAND” Gate
2–Input “NOR/OR” Gate
8–Input “AND/NAND” Gate
The MC14501UB is constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. These
complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired. Additional characteristics
can be found on the Family Data Sheet.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VDD DC Supply Voltage}
– 0.5 to + 18.0 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Iin, Iout Input or Output Current (DC or Transient),}
± 10
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{per Pin}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{PD Power Dissipation, per Packageâ€} 
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Tstg Storage Temperature}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _TL
Lead Temperature (8–Second Soldering)
500
mW
– 65 to + 150
_C
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CIRCUIT SCHEMATIC
VDD 16
VDD
11
13 (10) ₁₂
(6) 1
14
(7) 2
(9) 3
VSS
15
(5) 4
VSS 8
VSS
Numbers in parenthesis are for second 4–input gate.
MC14501UB
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
LOGIC DIAGRAM
(POSITIVE LOGIC)
1
2
3
4
11
12
5
6
7
9
VDD = PIN 16
VSS = PIN 8
13
14 AND
15 NAND
10
Use Dotted Connection Externally to
Obtain 8–Input AND/NAND
NOTE: Pin 14 must not be used as an input
NOTE: to the inverter.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14501UB
1