MC145003 Datasheet, PDF (1/14 Pages) Motorola, Inc – 128 SEGMENT LCD DRIVERS CMOS

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SEMICONDUCTOR TECHNICAL DATA
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128 Segment LCD Drivers
CMOS
MC145003
MC145004
The MC145003/5004 are 128–segment, multiplexed–by–four LCD Drivers.
The two devices are functionally the same except for their data input proto-
cols. The MC145003 uses an SPI data input protocol which is directly com-
patible with that of the MC6805 family of microcomputers. Using a minimal
amount of software (see example), the device may be interfaced to the
MC68HCXX product families. The MC145004 has a IIC interface and has es-
sentially the same protocol, except that the device sends an acknowledge bit
back to the transmitter after each eight–bit byte is received. MC145004 also
has a “read mode”, whereby data sent to the device may be retrieved via the
IIC bus.
The MC145003/MC145004 drives the liquid–crystal displays in a multi-
plexed–by–four configuration. The device accepts data from a microproces-
sor or other serial data source to drive one segment per bit. The chip does not
have a decoder, allowing for the flexibility of formatting the segment data
externally.
Devices are independently addressable via a two–wire (or three–wire)
communication link which can be common with other MC145003/MC145004
and/or other peripheral devices.
• Drives 128 Segments Per Package
• Devices May Be Cascaded for Larger LCD Applications
• May Be Used with the Following LCDs: Segmented Alphanumeric,
Bar Graph, Dot Matrix, Custom
• Quiscent Supply Current: 85 µA @ 2.8 V VDD
• Operating Voltage Range: 2.8 to 5.5 V
• Operating Temperature Range: – 40 to 85°C
• Separate Access to LCD Drive Section’s Supply Voltage to Allow for
Temperature Compensation
• See Application Notes AN1066 and AN442
52 1
QFP
FU SUFFIX
CASE 848B
ORDERING INFORMATION
MC145003FU QFP
MC145004FU QFP
PIN ASSIGNMENT
52 51 50 49 48 47 46 45 44 43 42 41 40
FP32 1
FP31 2
39 Din
38 DCLK
FP30 3
37 FS
FP29 4
36 FP1
FP28 5
35 FP2
FP27 6
34 FP3
FP26 7
33 FP4
FP25 8
32 FP5
FP24 9
31 FP6
FP23 10
30 FP7
FP22 11
29 FP8
FP21 12
28 FP9
FP20 13
27 FP10
14 15 16 17 18 19 20 21 22 23 24 25 26
BLOCK DIAGRAM
OSC1
OSC2
OSCILLATOR
VLCD ^BP1–BP4
DRIVERS
FP1–FP32
DRIVERS
NC = NO CONNECTION
FS
DCLK
Din
A0
A1
A2
ENB
FRAME
SYNC
GENERATOR
POR
LCD VOLTAGE
WAVEFORM
AND TIMING
GENERATOR
128–BIT LATCH
128 – 32
MULTIPLEX
128–BIT SHIFT REGISTER
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 1994
REV 1
12/94