MC14490 Datasheet, PDF (1/9 Pages) ON Semiconductor – Hex Contact Bounce Eliminator

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14490
Hex Contact Bounce Eliminator
The MC14490 is constructed with complementary MOS enhancement
mode devices, and is used for the elimination of extraneous level changes
that result when interfacing with mechanical contacts. The digital contact
bounce eliminator circuit takes an input signal from a bouncing contact and
generates a clean digital signal four clock periods after the input has
stabilized. The bounce eliminator circuit will remove bounce on both the
“make” and the “break” of a contact closure. The clock for operation of the
MC14490 is derived from an internal R–C oscillator which requires only an
external capacitor to adjust for the desired operating frequency (bounce
delay). The clock may also be driven from an external clock source or the
oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after power–up, the outputs of the MC14490 are in
indeterminate states.
• Diode Protection on All Inputs
• Six Debouncers Per Package
• Internal Pullups on All Data Inputs
• Can Be Used as a Digital Integrator, System Synchronizer, or Delay
Line
• Internal Oscillator (R–C), or External Clock Source
• TTL Compatible Data Inputs/Outputs
• Single Line Input, Debounces Both “Make” and “Break” Contacts
• Does Not Require “Form C” (Single Pole Double Throw) Input Signal
• Cascadable for Longer Time Delays
• Schmitt Trigger on Clock Input (Pin 7)
• Supply Voltage Range = 3.0 V to 18 V
• Chip Complexity: 546 FETs or 136.5 Equivalent Gates
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14490P
MC14490L
MC14490DW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
Ain 1
OSCin 7
OSCout 9
Bin 14
Cin 3
Din 12
Ein 5
Fin 10
+VDD
OSCILLATOR
AND
TWO–PHASE
CLOCK GENERATOR
BLOCK DIAGRAM
DATA
4–BIT STATIC SHIFT REGISTER
SHIFT LOAD
φ1
φ2
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
φ1 φ2
1/2–BIT
DELAY
φ1 φ2
15 Aout
VDD = PIN 16
VSS = PIN 8
2 Bout
13 Cout
4 Dout
11 Eout
6 Fout
REV 3
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©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14490
297