MC14194B Datasheet, PDF (1/6 Pages) Motorola, Inc – 4-Bit Bidirectional Universal Shift Register

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14194B
4-Bit Bidirectional Universal
Shift Register
The MC14194B is a 4–bit static shift register capable of operating in the
parallel load, serial shift left, serial shift right, or hold mode. The
asynchronous Reset input, when at a low level, overrides all other inputs,
resets all stages, and forces all outputs low. When Reset is at a logic 1 level,
the two mode control inputs, S0 and S1, control the operating mode as
shown in the truth table. Both serial and parallel operation are triggered on
the positive–going transition of the Clock input. The Parallel Data, Data Shift,
and mode control inputs must be stable for the specified setup and hold
times before and after the positive–going Clock transition.
• Synchronous Right/Left Serial Operation
• Synchronous Parallel Load
• Asynchronous Hold (Do Nothing) Mode
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• Functional Pin for Pin Equivalent of LS194}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VDD DCSupplyVoltage}
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Iin, Iout Input or Output Current (DC or Transient),}
± 10
mA
per Pin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{PD Power Dissipation, per Packageâ€} 
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Tstg Storage Temperature}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _TL
Lead Temperature (8–Second Soldering)
500
mW
– 65 to + 150
_C
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
S1 10
S0 9
3
DP0
LOGIC DIAGRAM
4
DP1
5
DP2
6
DP3
DSR 2
7
DSL
VDD = PIN 16
VSS = PIN 8
CLOCK 11
RESET 1
REV 3
1/94
©_MM_Cot₁or₄o₁la₉, I₄n_Bc. 1995
284
DQ
CR
Q0
15
DQ
CR
Q1
14
DQ
CR
Q2
13
DQ
CR
Q3
12
MOTOROLA CMOS LOGIC DATA