MC14094B Datasheet, PDF (1/6 Pages) ON Semiconductor – 8-Stage Shift/Store Register with Three-State Outputs

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Stage Shift/Store Register
with Three-State Outputs
The MC14094B combines an 8–stage shift register with a data latch for
each stage and a three–state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The QS output data is for use in
high–speed cascaded systems. The Q′_S output data is shifted on the
following negative clock transition for use in low–speed cascaded systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while strobe
is high.
Outputs of the eight data latches are controlled by three–state buffers
which are placed in the high–impedance state by a logic Low on Output
Enable.
• Three–State Outputs
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
• Input Diode Protection
• Data Latch
• Dual Outputs for Data Out on Both Positive and Negative Clock
Transitions
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ • Useful for Serial–to–Parallel Data Conversion
• Pin–for–Pin Compatible with CD4094B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VDD DC Supply Voltage}
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Iin, Iout Input or Output Current (DC or Transient),}
± 10
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{per Pin}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{PD Power Dissipation, per Packageâ€} 
500
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Tstg Storage Temperature}
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL
Lead Temperature (8–Second Soldering)
260
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{* Maximum Ratings are those values beyond which damage to the device may occur.}
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
Clock
Output
Enable
0
Strobe
X
Data
X
Parallel Outputs
Q1
QN
Z
Z
Serial Outputs
QS*
Q′_S
Q7 No Chg.
0
X
X
Z
Z
No Chg. Q7
1
0
X No Chg. No Chg. Q7 No Chg.
1
1
0
0
QN–1
Q7 No Chg.
1
1
1
1
QN–1
Q7 No Chg.
1
1
1 No Chg. No Chg. No Chg. Q7
Z = High Impedance X = Don’t Care
* At the positive clock edge, information in the 7th shift register stage is transferred to
Q8 and QS.
MC14094B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
PIN ASSIGNMENT
STROBE 1
DATA 2
CLOCK 3
Q1 4
Q2 5
Q3 6
Q4 7
VSS 8
16 VDD
15
OUTPUT
ENABLE
14 Q5
13 Q6
12 Q7
11 Q8
10 Q′_S
9 QS
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v v ^{operation, Vin and Vout should be constrained}
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14094B
1