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MC14093B Datasheet, PDF (1/6 Pages) ON Semiconductor – Quad 2-Input NAND Schmitt Trigger | |||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14077B Ä See Page 6-160
MC14078B, MC14081B, MC14082B Ä
See Page 6-5
MC14093B
Quad 2-Input NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS Pâchannel and
Nâchannel enhancement mode devices in a single monolithic structure.
These devices find primary use where low power dissipation and/or high
noise immunity is desired. The MC14093B may be used in place of the
MC14011B quad 2âinput NAND gate for enhanced noise immunity or to
âsquare upâ slowly changing waveforms.
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Capable of Driving Two LowâPower TTL Loads or One LowâPower
Schottky TTL Load Over the Rated Temperature Range
⢠Triple Diode Protection on All Inputs
⢠PinâforâPin Compatible with CD4093
⢠Can be Used to Replace MC14011B
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃà ⢠Independent SchmittâTrigger at each Input
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ MAXIMUM RATINGS* (Voltages Referenced to VSS)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Symbol
Parameter
Value
Unit
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ VDD DC Supply Voltage
â 0.5 to + 18.0
V
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Vin, Vout Input or Output Voltage (DC or Transient) â 0.5 to VDD + 0.5 V
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Iin, Iout Input or Output Current (DC or Transient),
± 10
mA
per Pin
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ PD Power Dissipation, per Packageâ
500
mW
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ Tstg Storage Temperature
â 65 to + 150
_C
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ TL
Lead Temperature (8âSecond Soldering)
260
_C
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ * Maximum Ratings are those values beyond which damage to the device may occur.
â Temperature Derating:
Plastic âP and D/DWâ Packages: â 7.0 mW/_C From 65_C To 125_C
Ceramic âLâ Packages: â 12 mW/_C From 100_C To 125_C
EQUIVALENT CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = â 55° to 125°C for all packages.
LOGIC DIAGRAM
1
2
3
5
6
4
8
9
10
12
13
11
VDD = PIN 14
VSS = PIN 7
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ⤠(Vin or Vout) ⤠VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14093B
1
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