MC14070B Datasheet, PDF (1/4 Pages) ON Semiconductor – CMOS SSI

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
MC14070B
MC14077B
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P–channel and N–channel
enhancement mode devices in a single monolithic structure. These
complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• MC14070B — Replacement for CD4030B and CD4070B Types}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• MC14077B — Replacement for CD4077B Type}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VDD DC Supply Voltage}
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Iin, Iout Input or Output Current (DC or Transient),}
± 10
mA
per Pin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{PD Power Dissipation, per Packageâ€} 
500
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Tstg Storage Temperature}
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^TL
Lead Temperature (8–Second Soldering)
260
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{* Maximum Ratings are those values beyond which damage to the device may occur.}
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
20 ns
20 ns
VDD
90%
VDD
50%
IDD
Vin
10%
VSS
1/f
Vin
*
50% DUTY CYCLE
CL
* Inverted output on MC14077B only.
Figure 1. Power Dissipation Test Circuit and Waveform
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
MC14070B
MC14077B
QUAD Exclusive OR QUAD Exclusive NOR
Gate
Gate
1
1
3
3
2
2
5
5
4
4
6
6
8
8
10
10
9
9
12
12
11
11
13
13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
VDD
20 ns
PULSE
GENERATOR
#
*
VSS
INPUT
90%
50%
10%
CL
tPHL
OUTPUT
90%
50%
10%
tTHL
* Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
Figure 2. Switching Time Test Circuit and Waveforms
20 ns
VDD
VSS
tPLH
VOH
VOL
tTLH
PIN ASSIGNMENT
IN 1A 1
IN 2A 2
OUTA 3
OUTB 4
IN 1B 5
IN 2B 6
VSS 7
14 VDD
13 IN 2D
12 IN 1D
11 OUTD
10 OUTC
9 IN 2C
8 IN 1C
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14070B MC14077B
1