MC14027B Datasheet, PDF (1/6 Pages) Motorola, Inc – Dual J-K Flip-Flop

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14025B (see Page 6-5)
MC14025UB (see Page 6-14)
Dual J-K Flip-Flop
The MC14027B dual J–K flip–flop has independent J, K, Clock (C), Set (S)
and Reset (R) inputs for each flip–flop. These devices may be used in
control, register, or toggle functions.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going edge
of the clock pulse
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{• Pin–for–Pin Replacement for CD4027B}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{MAXIMUM RATINGS* (Voltages Referenced to VSS)}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{VDD DC Supply Voltage}
– 0.5 to + 18.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V}
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{lin, lout Input or Output Current (DC or Transient),}
± 10
mA
per Pin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{PD Power Dissipation, per Packageâ€} 
Tstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _TL
Lead Temperature (8–Second Soldering)
500
mW
– 65 to + 150
_C
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
C†
J
1
X
0
X
1
X
X
X
X
X
X
X
X = Don’t Care
† _{= Level Change}
TRUTH TABLE
Inputs
Outputs*
K
S
R
Qn‡ Qn+1 Qn+1
X
0
0
0
1
0
0
0
0
1
1
0
X
0
0
0
0
1
1
0
0
1
0
1
1
0
0
Qo
Qo
Qo
X
0
0
X
Qn
Qn
X
1
0
X
1
0
X
0
1
X
0
1
X
1
1
X
1
1
‡ _{= Present State}
* = Next State
No
Change
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14027B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
7
6
J ^SQ
1
3C
5K
Q2
R
4
9
10
J ^SQ
15
13 C
11 K
Q 14
R
12
VDD = PIN 16
VSS = PIN 8
MC14027B
107