MC10LVELT23 Datasheet, PDF (1/3 Pages) Motorola, Inc – Dual Differential LVPECL to TTL Translator

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SEMICONDUCTOR TECHNICAL DATA
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Dual Differential LVPECL to
TTL Translator
The MC100LVELT23 is a dual differential LVPECL to TTL translator.
Because LVPECL (Positive ECL) levels are used only +3.3V and ground
are required. The small outline 8-lead SOIC package and the dual gate
design of the LVELT23 makes it ideal for applications which require the
translation of a clock and a data signal.
The LVELT23 is available in only the ECL 100K standard. Since there
are no LVPECL outputs or an external VBB reference, the LVELT23 does
not require both ECL standard versions. The LVPECL inputs are
differential; there is no specified difference between the differential input
10H and 100K standards. Therefore, the MC100LVELT23 can accept any
standard differential LVPECL input referenced from a VCC of 3.3V.
• 2.0ns Typical Propagation Delay
• Differential LVPECL Inputs
• Small Outline SOIC Package
• 24mA TTL Outputs
• Flow Through Pinouts
• ESD Performance: Human Body Model 1200V; Machine Model 150V
Note:
1) Pulling the output higher than VCC is not recommended. Doing so
causes excessive leakage and possible latchup leading to reliability
risk.
D0 1
D0 2
LVPECL
D1 3
8 VCC
7 Q0
TTL
6 Q1
D1 ⁴
5 _GND
Figure 1. 8–Lead Pinout and Logic Diagram
MC100LVELT23
D SUFFIX
8–LEAD PLASTIC SOIC PACKAGE
CASE 751–05
PIN DESCRIPTION
PIN
Qn
Dn
VCC
GND
FUNCTION
TTL Outputs
Diff LVPECL Inputs
+3.3V Supply
Ground
This document contains information on a product under development. Motorola reserves the right to
change or discontinue this product without notice.
3/98
© Motorola, Inc. 1998
3–1
REV 0.2