MC10H181 Datasheet, PDF (1/5 Pages) ON Semiconductor – 4-BIT ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Bit Arithmetic Logic Unit/
Function Generator
MC10H181
The MC10H181 is a high–speed arithmetic logic unit capable of performing
16 logic operations and 16 arithmetic operations on two four–bit words. Full
internal carry is incorporated for ripple through operation.
Arithmetic logic operations are selected by applying the appropriate binary
word to the select inputs (S0 through S3) as indicated in the tables of
arithmetic/logic functions. Group carry propagate (PG) and carry generate (GG)
are provided to allow fast operations on very long words using a second order
look–ahead. The internal carry is enabled by applying a low level voltage to the
mode control input (M).
When used with the MC10H179, full–carry look–ahead, as a second order
look–ahead block, the MC10H181 provides high–speed arithmetic operations
on very long words.
This 10H part is a functional/pinout duplication of the standard MECL 10K
family part with 100% improvement in propagation delay and no increase in
power supply current.
• Improved Noise Margin, 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K – Compatible
MAXIMUM RATINGS
Characteristic
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
Symbol
Rating
Unit
VEE
VI
Iout
–8.0 to 0
Vdc
0 to VEE
Vdc
50
mA
100
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
13
15
17
14
S0 S1 S2 S3
21
A0
F0
20
B0
F1
18
A1
19
B1
F2
16
A2
F3
11
B2
10
A3
GG
9
B3
22
Cn
PG
23
M
Cn+4
FUNCTION SELECT TABLE
Function Select
S3 S2 S1 S0
Logic Functions
M is High C = D.C.
F
LLLL
L L LH
L LHL
L LHH
LHL L
2L ^{H L H}
L HH L
3L _{H H H}
7H ^{L L L}
HL LH
6H _{L H L}
4H ^{L H H}
HHL L
8H _{H L H}
5H ^{H H L}
HHHH
F=A
F=A+B
F=A+B
F = Logical “1”
F=A•B
F=B
 F = A B
F=A+B
F=A•B
 F = A B
F=B
F=A+B
F = Logical “0”
F=A•B
F=A•B
F=A
Arithmetic Operation
M is Low Cn is low
F
F=A
F = A plus (A • B)
F = A plus (A • B)
F = A times 2
F = (A + B) plus 0
F = (A + B) plus (A • B)
F = A plus B
F = A plus (A + B)
F = (A + B) plus 0
F = A minus B minus 1
F = (A + B) plus (A • B)
F = A plus (A + B)
F = minus 1 (two’s complement)
F = (A • B) minus 1
F = (A • B) minus 1
F = A minus 1
L SUFFIX
CERAMIC PACKAGE
CASE 758–02
P SUFFIX
PLASTIC PACKAGE
CASE 724–03
FN SUFFIX
PLCC
CASE 776–02
DIP
PIN ASSIGNMENT
VCC1
1
24
VCC2
F0
2
23
M
F1
3
22
CN
GG
4
CN _{+ 4}
5
21
A0
20
B0
F3
6
19
B1
F2
7
18
A1
PG
8
17
S1
B3
9
16
A2
A3
10
15
S2
B2
11
14
S0
VEE
12
13
S3
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
9/96
© Motorola, Inc. 1996
2–275
REV 6